1. Field of the Invention
The present invention discloses a circuit testing device and testing method thereof, and more particularly a register circuit utilized in a Domino CMOS logic circuit, a scanning register circuit that utilizes the register circuit and a method thereof.
2. Description of the Prior Art
In the field of digital logic circuits, circuit designers replace static circuits with dynamic circuits in order to increase the operating frequency of the circuit, wherein the dynamic circuit includes a domino CMOS logic circuit, a differential cascade voltage swing logic, etc. The domino CMOS logic circuit will herein be taken as an example. The domino CMOS logic circuit comprises a pseudo NMOS configuration to implement the domino CMOS logic circuit. Therefore, compared to the static circuit, using a pseudo NMOS configuration in the domino CMOS logic circuit will greatly reduce the number of transistors. Furthermore, the domino CMOS logic circuit has much less pull-up delay and a negligible short-circuit current effect when undergoing a dynamic operation. Therefore, using the domino CMOS logic circuit to implement a dynamic circuit is a more compatible method when designing an integrated circuit.
In reality, however, the above-mentioned domino CMOS logic circuit has a major problem when testing the dynamic circuit. In the prior art, the testing method can only test the dynamic circuit under the assumption that the domino CMOS logic circuit is comprised of purely combinational Domino gates, and the testing method is not appropriate for sequential Domino logic. Thus, most circuit designers nowadays prefer to use a combination of the dynamic circuit and the static circuit.
According to U.S. Pat. No. 6,108,805 “DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUTS”, such a system has at least three disadvantages. Firstly, because the output stage of the prior art domino CMOS logic circuit is comprised of multiple stages, the time required for generating an output data from an input data is longer. Secondly, because the prior art utilizes two control clocks, a system clock and a Domino clock in the operating procedure, the timing between the system clock and the Domino clock has to be precisely controlled to obtain the output data. Thirdly, the duty cycle of the system clock and Domino clock utilized by the prior art are different, which will complicate the implementation of the circuit.